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AD734AN View Datasheet(PDF) - Analog Devices

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AD734AN Datasheet PDF : 20 Pages
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AD734
X INPUT
U1
U INPUT
2M
AD734
1 X1
VP 14
2 X2
DD 13
3 U0
W 12
4 U1
Z1 11
+15V
0.1µF W = (X1 – X2)(Y1 – Y2) + Z2
U1 – U2
LOAD
L GROUND
U2
Y INPUT
5 U2
6 Y1
7 Y2
Z2 10
ER 9 NC
VN 8
0.1µF
–15V
Z2
L OPTIONAL
SUMMING
INPUT
±10V FS
Figure 29. Three-Variable Multiplier/Divider Using Direct Denominator
Control
This connection scheme can also be viewed as a variable-gain
element, whose output, in response to a signal at the X input, is
controllable by both the Y input (for attenuation, using Y less
than U) and the U input (for amplification, using U less than
Y). The ac performance is shown in Figure 30; for these results,
Y was maintained at a constant 10 V. At U = 10 V, the gain is
unity and the circuit bandwidth is a full 10 MHz. At U = 1 V,
the gain is 20 dB and the bandwidth is essentially unaltered. At
U = 100 mV, the gain is 40 dB and the bandwidth is 2 MHz.
Finally, at U = 10 mV, the gain is 60 dB and the bandwidth is
250 kHz, corresponding to a 250 MHz gain-bandwidth product.
70
U = 10mV
60
50
U = 100mV
40
30
U = 1V
20
10
U = 10V
0
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 30. Three-Variable Multiplier/Divider Performance
The 2 MΩ resistor is included to improve the accuracy of the
gain for small denominator voltages. At high gains, the X input
offset voltage can cause a significant output offset voltage. To
eliminate this problem, a low-pass feedback path can be used
from W to X2; see Figure 32 for details.
Where a numerator of 10 V is needed, to implement a two-
quadrant divider with fixed scaling, the connections shown in
Figure 31 can be used. The reference voltage output appearing
between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered by
the second op amp, to impose 10 V across the Y1/Y2 input.
Note that Y2 is connected to the negative supply in this application.
This is permissible because the common-mode voltage is still
high enough to meet the internal requirements.
The transfer function is
W
=
10
V
⎜⎛
⎜⎝
X1
U1
X2
U2
⎟⎞
⎟⎠
+
Z2
(12)
The ac performance of this circuit remains as shown in Figure 30.
X INPUT
U1
U INPUT
U2
2M
200k
100k
SCALE
AJDUST
AD734
1 X1
VP 14
2 X2
DD 13
3 U0
W 12
4 U1
Z1 11
5 U2
Z2 10
6 Y1
ER 9
7 Y2
VN 8
+15V
0.1µF W = (X1 – X2)10V + Z2
U1 – U2
LOAD
L GROUND
Z2
0.1µF L OPTIONAL
SUMMING
INPUT
–15V
±10V FS
OP AMP = AD712 DUAL
Figure 31. Two-Quadrant Divider with Fixed 10 V Scaling
A PRECISION AGC LOOP
The variable denominator of the AD734 and its high gain
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 32 shows a
suggested method. The input signal, EIN, which can have a peak
amplitude from 10 mV to 10 V at any frequency from 100 Hz to
10 MHz, is applied to the X input and a fixed positive voltage EC
to the Y input. Op Amp A2 and Capacitor C2 form an integrator
with a current summing node at its inverting input. (The AD712
dual op amp is a suitable choice for this application.) In the absence
of an input, the current in D2 and R2 causes the integrator output
to ramp negative, clamped by Diode D3, which is included to
reduce the time required for the loop to establish a stable,
calibrated, output level after the circuit has received an input
signal. With no input to the denominator (U0 and U2), the gain
of the AD734 is very high (about 70 dB), and thus even a small
input causes a substantial output.
C1
1µF
EIN
R3
1M
A1
+15V
AD734
1 X1
VP 14
2 X2
3 U0
DD 13
W 12
0.1µF D1
1N914
D3
1N914
EC
+1V TO
+10V
C2
1µF
A2 NC 4 U1
5 U2
6 Y1
D2
1N914
7 Y2
Z1 11
Z2 10
ER 9
C1
L
1µF
L
0.1µF
VN 8
–15V
EOUT
R2
1M
R1
1M
OP AMP = AD712 DUAL
Figure 32. Precision AGC Loop
Diode D1 and C1 form a peak detector, which rectifies the output
and causes the integrator to ramp positive. When the current in
R1 balances the current in R2, the integrator output holds the
denominator output at a constant value. This occurs when there
Rev. E | Page 15 of 20
 

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