MC1401 View Datasheet(PDF) - PMD
Part Name
Description
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MC1401 Datasheet PDF : 70 Pages
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Timing Interval
Command Byte Write Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
Host Cmd Hold Time
HostRdy Delay Time
~HostWrite Pulse Width
Write Data Setup Time
Write Data Hold Time
Data Word Read Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
HostCmd Hold Time
Read Data Access Time
Read Data Hold Time
~HostRead high to HI-Z Time
HostRdy Delay Time
Read Recovery Time
Data Word Write Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
HostCmd Hold Time
HostRdy Delay Time
~HostWrite Pulse Width
Write Data Setup Time
Write Data Hold Time
Write Recovery Time
DAC Interface Timing
I/OAddr Stable to ~I/OWrite setup time
~I/OWrite Pulse Width
Data Hold Time After ~I/OWrite
ClkOut Low to I/OAddr stable
ClkOut Low to ~I/OWrite Low
ClkOut Low to Data Valid
ClkOut Cycle Time
I/OAddr Stable to DACSlct High
~I/OWrite Low to DACSlct High
PWM Output Timing
PWM Output Frequency
T#
Min.
T6
15
T7
10
T8
10
T9
25
T13
T14
50
T15
35
T16
30
T6
15
T7 (read only)
- 20
T8 (read only)
- 20
T9
25
T10
T11
10
T12
T13
T17
60
T6
15
T7
10
T8
10
T9
25
T13
T14
50
T15
35
T16
30
T18
60
T19
35
T20
56
T21
17
T22
10
T23
75
T24
T25
T26
T27
24.5
Max.
2000 (note 3)
70
2000 (note 3)
50
50
70
2000 (note 3)
70
95
40
92
92
160 typical (note 4)
66
44.5
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Khz
note 1
note 2
note 3
note 4
~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met.
Chip-set performance figures and timing information valid at Fclk = 25.0 only. For timing information & performance parameters at Fclk <
25.0 Mhz, call PMD.
Two micro seconds maximum to release interface before chip set responds to command
ClkOut from CP is 1/4 frequency of ClkIn (CP chip).
6
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