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11525-801 View Datasheet(PDF) - AMI Semiconductor

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11525-801 Datasheet PDF : 26 Pages
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3.2 Stop Clock Control
Three pins control the clock outputs: CPU_STOP#,
PCI_STOP# and PWR_DWN#.
3.2.1 CPU-Enable, PCI-Enable
The CPU_STOP# pin is an active-low LVTTL input pin
that disables the CPU_0:3 clocks for low power opera-
tion. CPU_STOP# can be asserted asynchronously, and
the stop clock control is glitch-free, in that the CPU clock
must complete a full cycle before the clock is stopped
low.
The PCI_STOP# pin is an active-low LVTTL input pin that
disables the PCI_1:7 clocks for low power operation, ex-
cept for the PCI_F clock. The PCI_F is a free-running
clock, and will continue to run even if all other PCI clocks
have stopped. PCI_STOP# can be asserted asynchro-
nously, and the stop-clock control is glitch-free, in that the
PCI clock must complete a full cycle before the clock is
stopped low.
3.2.2 Power Down
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that puts the device in a low power inactive
state without removing power from the device. All internal
clocks are turned off, and all clock outputs are held low.
Powering down occurs in less than two PCI clocks from
the falling edge of PWR_DWN# to when all clock outputs
are forced low.
4.0 Clock Latency
All clock outputs are stopped in the low state, and are
started so that the first high pulse is a full pulse width. All
clocks complete a full period on transitions between run-
ning (enabled) and stopped (disabled) to ensure glitch-
free stop clock control.
All enabled clocks will continue to run while disabled
clocks are stopped. The clock enable signals are as-
sumed to be asynchronous inputs relative to clock out-
puts. Enable signals are synchronized to their respective
clocks by this device. The CPU and PCI clocks will tran-
sition between running and stopped according to Table 5.
4.1 Power-Up Latency
Power-up latency is defined as the time from the moment
when PWR_DWN# goes inactive (a rising edge) to when
the first valid clocks are driven from the device. Upon re-
lease of PWR_DWN#, external circuitry should allow a
minimum of 3ms for the PLLs to lock before enabling any
clocks.
4.2 Clock Enable Latency
Clock enable latency is defined in the number of rising
edges of free-running CPU clocks between when the en-
able signal becomes active (a rising edge) to when the
first valid clock is driven from the device.
Figure 2: CPU_STOP# Timing
CPU clock
(internal)
PCI clock
(internal)
CPU_STOP#
CPU_0:3
4.5.99
,62
4
 

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