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ADS6616A4A-6 View Datasheet(PDF) - A-Data Technology

Part NameDescriptionManufacturer
ADS6616A4A-6 Synchronous DRAM 1M x 16 Bit x 4 Banks A-Data
A-Data Technology A-Data
ADS6616A4A-6 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
A-Data
Synchronous DRAM
ADS6616A4A
1M x 16 Bit x 4 Banks
General Description
The ADS6616A4A are four-bank Synchronous
DRAMs organized as 1,048,576 words x 16 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
JEDEC standard LVTTL 3.3V power supply
MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
4 banks operation
All inputs are sampled at the positive edge of
the system clock
Burst Read single write operation
Auto & Self refresh
4096 refresh cycle
DQM for masking
Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
ADS6616A4A-5
ADS6616A4A-6
ADS6616A4A-7
ADS6616A4A-7.5
Pin Assignment
Frequency
200Mhz
166Mhz
143Mhz
133Mhz
VDD
DQ0
VDDQ
DQ1
DQ2
VSS
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
Interface
LVTTL
LVTTL
LVTTL
LVTTL
Package
400mil 54pin TSOPII
400mil 54pin TSOPII
400mil 54pin TSOPII
400mil 54pin TSOPII
1
54
Vss
2
53
DQ15
3
52
VssQ
4
51
DQ14
5
50
DQ13
6
49
VDDQ
7
48
DQ12
8
47
DQ11
9
46
VSSQ
10
45
DQ10
11
44
DQ9
12
43
VDDQ
13
42
DQ8
14
41
VSS
15
40
NC
16
39
UDQM
17
38
CLK
18
37
CKE
19
36
NC
20
35
A11
21
34
A9
22
33
A8
23
32
A7
24
31
A6
25
30
A5
26
29
A4
27
28
VSS
54-pin plastic TSOP II 400 mil
Rev 1.1 April, 2001
1
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