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N04Q1612C2BT2-70C View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
N04Q1612C2BT2-70C 4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction ETC
Unspecified 
N04Q1612C2BT2-70C Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
NanoAmp Solutions, Inc.
Power Savings with Page Mode Operation (WE = VIH)
N04Q16yyC2B
Advance Information
Page Address
(A0, A5-A17)
Word Address
(A1-A4)
CE1
CE2
OE
LB, UB
Word 1
Open page
Word 2
...
Word 16
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A1 - A4 as the least
significant bits and addressing the 16 words within the open page, power is reduced to the page mode
value which is considerably lower than standard operating currents for low power SRAMs.
Stock No. 23451-B 2/06
6
The specification is ADVANCE INFORMATION and subject to change without notice.
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