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ST6201CB1 View Datasheet(PDF) - STMicroelectronics

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ST6201CB1 Datasheet PDF : 100 Pages
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ST6200C ST6201C ST6203C
A/D CONVERTER (Cont’d)
8.3.4 Recommendations
The following six notes provide additional informa-
tion on using the A/D converter.
1.The A/D converter does not feature a sample
and hold circuit. The analog voltage to be meas-
ured should therefore be stable during the entire
conversion cycle. Voltage variation should not ex-
ceed ±1/2 LSB for optimum conversion accuracy.
A low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
2. When selected as an analog channel, the input
pin is internally connected to a capacitor Cad of
typically 9pF. For maximum accuracy, this capaci-
tor must be fully charged at the beginning of con-
version. In the worst case, conversion starts one
instruction (6.5 µs) after the channel has been se-
lected. The impedance of the analog voltage
source (ASI) in worst case conditions, is calculat-
ed using the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband.
The ASI can be higher if Cad has been charged for
a longer period by adding instructions before the
start of conversion (adding more than 26 CPU cy-
cles is pointless).
3. Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
4. Conversion accuracy depends on the quality of
the power supplies (VDD and VSS). The user must
take special care to ensure a well regulated refer-
ence voltage is present on the VDD and VSS pins
(power supply voltage variations must be less than
0.1V/ms). This implies, in particular, that a suitable
decoupling capacitor is used at the VDD pin.
The converter resolution is given by:
V-----D-----D----------V----S-----S--
256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
5. Conversion resolution can be improved if the
power supply voltage (VDD) to the microcontroller
is lowered.
6. In order to optimize the conversion resolution,
the user can configure the microcontroller in WAIT
mode, because this mode minimises noise distur-
bances and power supply variations due to output
switching. Nevertheless, the WAIT instruction
should be executed as soon as possible after the
beginning of the conversion, because execution of
the WAIT instruction may cause a small variation
of the VDD voltage. The negative effect of this var-
iation is minimized at the beginning of the conver-
sion when the converter is less sensitive, rather
than at the end of conversion, when the least sig-
nificant bits are determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In
this case only the ADC peripheral and the oscilla-
tor are then still working. The MCU must be woken
up from WAIT mode by the ADC interrupt at the
end of the conversion. The microcontroller can
also be woken up by the Timer interrupt, but this
means the Timer must be running and the result-
ing noise could affect conversion accuracy.
Caution: When an I/O pin is used as an analog in-
put, A/D conversion accuracy will be impaired if
negative current injections (VINJ < VSS) occur from
adjacent I/O pins with analog input capability. Re-
fer to Figure 29. To avoid this:
– Use another I/O port located further away from
the analog pin, preferably not multiplexed on the
A/D converter
– Increase the input resistance RIN J (to reduce the
current injections) and reduce RADC (to preserve
conversion accuracy).
Figure 29. Leakage from Digital Inputs
Digital
Input
RINJ PBy/AINy
I/O Port
(Digital I/O)
VINJ
Analog
Input
RADC
Leakage Current
if VINJ < VSS
PBx/AINx
A/D
Converter
VAIN
50/100
1
Doc ID 4563 Rev 5
 

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