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ST6201CN6 View Datasheet(PDF) - STMicroelectronics

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ST6201CN6 Datasheet PDF : 100 Pages
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ST6200C ST6201C ST6203C
8 ON-CHIP PERIPHERALS
8.1 WATCHDOG TIMER (WDG)
8.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the SR bit be-
comes cleared.
Figure 25. Watchdog Block Diagram
8.1.2 Main Features
Programmable timer (64 steps of 3072 clock
cycles)
Software reset
Reset (if watchdog activated) when the SR bit
reaches zero
Hardware or software watchdog activation
selectable by option bit (Refer to the option
bytes section)
RESET
WATCHDOG REGISTER (WDGR)
T0 T1 T2 T3 T4 T5 SR C
bit 7
7-BIT DOWNCOUNTER
bit 0
fint /12
CLOCK DIVIDER
÷ 256
Doc ID 4563 Rev 5
41/100
1
 

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