ST6200C ST6201C ST6203C
5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources:
– external clock signal
– external AT-cut parallel-resonant crystal
– external ceramic resonator
– external RC network (RNET).
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in the event of main oscil-
lator failure. It also automatically limits the internal
clock frequency (fINT) as a function of VDD, in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
Figure 9. Clock Circuit Block Diagram
Table 5 illustrates various possible oscillator con-
figurations using an external crystal or ceramic
resonator, an external clock input, an external re-
sistor (RNET), or the lowest cost solution using only
For more details on configuring the clock options,
refer to the Option Bytes section of this document.
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the Watchdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.
With an 8 MHz oscillator, the fastest CPU cycle is
A CPU cycle is the smallest unit of time needed to
execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.
OSCILLATOR SAFEGUARD (OSG)
(ADCR REGISTER) *
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)
* Depending on device. See device summary on page 1.
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