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ST62E03CN1 View Datasheet(PDF) - STMicroelectronics

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ST62E03CN1 Datasheet PDF : 100 Pages
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ST6200C ST6201C ST6203C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
080h
to 083h
0C0h
0C1h
CPU
I/O Ports
X,Y,V,W
DRA 1) 2) 3)
DRB 1) 2) 3)
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
xxh
R/W
00h R/W
00h R/W
0C2h
0C3h
0C4h
0C5h
I/O Ports
DDRA 2)
DDRB 2)
Reserved (2 Bytes)
Port A Direction Register
Port B Direction Register
00h R/W
00h R/W
0C6h
0C7h
Reserved (2 Bytes)
0C8h
CPU
IOR
Interrupt Option Register
xxh
Write-only
0C9h
ROM
DRWR
Data ROM Window register
xxh
Write-only
0CAh
0CBh
0CCh
0CDh
I/O Ports
ORA 2)
ORB 2)
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
00h R/W
00h R/W
0CEh
0CFh
Reserved (2 bytes)
0D0h
0D1h
ADC
ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh
Read-only
40h Ro/Wo
0D2h
0D3h
0D4h
Timer 1
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
7Fh R/W
0FFh R/W
00h
R/W
0D5h
to 0D7h
Reserved (3 Bytes)
0D8h
Watchdog
Timer
WDGR
Watchdog Register
0FEh R/W
0D9h
to 0FEh
Reserved (38 Bytes)
0FFh
CPU
A
Accumulator
xxh
R/W
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 7 "I/O PORTS" on page 36 for more details).
4. Depending on device. See device summary on page 1.
Doc ID 4563 Rev 5
11/100
1
 

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