ISL6260 View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL6260

Multiphase Core Regulator for IMVP-6 Mobile CPUs

Intersil 

ISL6260, ISL6260B

PWM2

PWM output for channel 2. For ISL6260B, PSI# low will

make this output tri-state.

PWM1

PWM output for channel 1.

VID0, VID1, VID2, VID3, VID4, VID5, VID6

VID input with VID0 = LSB.

CLK_EN#

Digital output to enable System PLL Clock; Goes active

10µs after PG_IN is active and Vcore is within 10% of Boot

Voltage.

PGOOD

Power Good open-drain output. Will be pulled up externally

by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.

3V3

3.3V supply voltage for CLK_EN# logic, such an

implementation will improve power consumption from 3.3V

compared to open drain circuit other wise.

VR_ON

Voltage Regulator enable input. A high level logic signal on

this pin enables the regulator.

DPRSLPVR

Deeper Sleep Enable signal. A high level logic signal on this

pin indicates that the micro-processor is in Deeper Sleep

Mode and indicates that slow entry and exit from C4 should

occur. DPRSLPVR low indicates large charging or

discharging soft pin current, and therefore fast output

voltage transitions.

DPRSTP#

Deeper Sleep Enable signal. A low level logic signal on this

pin indicates that the micro-processor is in Deeper Sleep

Mode.

3

FN9162.1

January 3, 2006

Share Link: