ISL12021 View Datasheet(PDF) - Intersil
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ISL12021 Datasheet PDF : 24 Pages
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ISL12021
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ pin when the RTC is triggered
by the alarm as defined by the alarm registers (0Ch to 11h).
When the IM bit is cleared to “0”, the alarm will operate in
standard mode, where the IRQ pin will be set low until the
ALM status bit is cleared to “0”.
TABLE 4.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the FOUT and IRQ pins during
battery backup mode (i.e. VBAT power source active). When
the FOBATB is set to “1” the FOUT and IRQ pins are
disabled during battery backup mode. This means that both
the frequency output and alarm output functions are
disabled. When the FOBATB is cleared to “0”, the FOUT and
IRQ pins are enabled during battery backup mode. Note that
the open drain FOUT and IRQ pins will need a pullup to the
battery voltage to operate in battery backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the FOUT pin. See Table 5 for
frequency selection. .
TABLE 5. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS FO3
FO2 FO1 FO0
0
Hz
0
0
0
0
32768
Hz
0
0
0
1
4096
Hz
0
0
1
0
1024
Hz
0
0
1
1
64
Hz
0
1
0
0
32
Hz
0
1
0
1
16
Hz
0
1
1
0
TABLE 5. FREQUENCY SELECTION OF FOUT PIN (Continued)
FREQUENCY,
FOUT
UNITS FO3
FO2 FO1 FO0
8
Hz
0
1
1
1
4
Hz
1
0
0
0
2
Hz
1
0
0
1
1
Hz
1
0
1
0
1/2
Hz
1
0
1
1
1/4
Hz
1
1
0
0
1/8
Hz
1
1
0
1
1/16
Hz
1
1
1
0
1/32
Hz
1
1
1
1
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
ADDR 7 6 5 4 3
2
1
0
09h CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0
This bit clears Time Stamp VDD to Battery (TSV2B) and
Time Stamp Battery to VDD Registers (TSB2V). The default
setting is 0 (CLRTS = 0) and the Enabled setting is 1
(CLRTS = 1)
VDD Brown Out Trip Voltage BITS (VDDTrip)<2:0
These bits set the 6 trip levels for the VDD alarm, indicating
that VDD has dropped below a preset level, in this event, the
LVDD bit in the Status Register is set to “1”. See Table 6.
TABLE 6. VDD TRIP LEVELS
VDDTrip2
0
VDDTrip1
0
VDDTrip0
0
TRIP
VOLTAGE
(V)
2.295
0
0
1
2.550
0
1
0
2.805
0
1
1
3.060
1
0
0
4.250
1
0
1
4.675
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two VBAT alarms,
with levels set to approximately 85% and 75% of the nominal
battery level.
TABLE 7.
ADDR 7 6 5
4
3
2
1
0
0Ah BSW 0 VB85 VB85 VB85 VB75 VB75 VB75
Tp2 Tp1 Tp0 Tp2 Tp1 Tp0
13
FN6451.0
March 30, 2007
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