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MAX785 View Datasheet(PDF) - Maxim Integrated

Part Name
Description
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MAX785
MaximIC
Maxim Integrated MaximIC
MAX785 Datasheet PDF : 24 Pages
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Product Reliability Report
_______________________________________________________________________Process Technologies
This section defines the layer-by-layer construction steps used in the fabrication of each process.
(1) SMG (Refer to Figure 1)
Layer Description
1
P-Well Diffusion
2
P+ Diffusion
3
N+ Diffusion
4
Gate-Oxide Growth
5
Threshold Implant
6
Contact Etch
7
Metallization
8
Passivation
(2) MV1 (Refer to Figure 2)
Layer Description
0
Buried Layer
1
EPI Deposit
2
P-Well Diffusion
3
P+ Diffusion
4
N+ Diffusion
5
Gate-Oxide Growth
6
Threshold Implant
7
Contact
8
Metallization
9
Passivation
(3) MV2 (Refer to Figure 3)
Layer Description
1
Buried Layer
2
P Well
3
P+ Diffusion
4
N+ Diffusion
5
Gate-Oxide Growth
6
P-Ch Threshold Adjust
7
Polysilicon
8
NLDD
9
PLDD
10
N+ Ohmic
11
Contact
12
Metal
13
Passivation
(4) SG3 (Refer to Figure 4)
Layer Description
1
P Well
2
PNP Base
3
Zener Implant
4
Active Area
5
P Guard
6
N Guard
7
P-Ch Threshold Adjust
8
Poly 2
9
Poly 1
10
N+ Block
11
P+ Select
12
Thin Film
13
CrSi Contact
14
Contact
15
Metal
16
Passivation
Dimension
10µm
2µm
2µm
900Å
1µm (Al, Si-1%)
0.8µm (Si3N4 over SiO2)
Dimension
10µm
19µm
10µm
3µm
3µm
1975Å
1µm (Al, Si-1%)
0.8µm (Si3N4 over SiO2)
Dimension
24.0µm
10.0µm
1.5µm
1.5µm
1000Å
4500Å
1.0µm
0.8µm
Dimension
6.0µm
1.5µm
7000Å
4000Å
1.0µm
0.8µm (Si3N4 over SiO2)
(5) SG5 (Refer to Figure 5)
Layer Description
Dimension
1
P-Well Diffusion
8µm
2
PNP Base Drive
3
Zener Implant
4
Active Area/Field Ox
1µm
5
N Guard
6
P Guard
7
Threshold Adjust
8
Gate-Oxide Growth
750Å
9
Polysilicon 1
4400Å
10
Cap Oxide
1000Å
11
Polysilicon 2
4400Å
12
N+ Implant (Source/Drain)
13
P+ Implant (Source/Drain)
14
Chrome/Si Thin-Film Deposit
15
Contact
16
Metallization
1µm
17
Passivation
0.8µm (Si3N4 over SiO2)
(6) SG1.2 (Refer to Figure 6)
Layer Description
0
Mark Layer on P Substrate
1
N+ Buried Layer
2
P+ Buried Layer
3
P Well
4
NPN Base
5
PNP Base
6
Active Area
7
P Guard
8
N Guard
9
Gate-Oxide Growth
10
Poly 1
11
Poly 2
12
NMOS LDD
13
N+ Implant (Source/Drain)
14
P+ Implant (Source/Drain)
15
Thin Film (Chrome/Si)
16
Contact
17
TF Contact
18
Metal 1
19
Metal 1 Options
20
Via
21
Metal 2
22
Passivation
Dimension
4µm
6µm
2.8µm
230Å
4200Å
4200Å
0.3µm
0.3µm
6000Å
1.0µm
8000Å
(7) BIP (Refer to Figure 7)
Layer Description
1
N+ Buried Layer
2
P+ Isolation
3
P Base
4
N+ Emitter
5
Capacitor
6
Contact Etch
7
Aluminum
8
Passivation
Dimension
4.5µm
20µm
3µm
2.5µm
1500Å
11kÅ (Al, Si-1%)
8kÅ (Si3N4 over SiO2)
4 ______________________________________________________________________________________
 

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