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GT-6816 View Datasheet(PDF) - Unspecified

Part Name
Description
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GT-6816
ETC
Unspecified ETC
GT-6816 Datasheet PDF : 63 Pages
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GT-6816
Interrupt Select Register
CPU Read/Write
Address: FFB0H
Bits Reset
Description
7
0 Select USB interrupt enable register or USB interrupt status register to read or write.
0: USB interrupt status register 1A and USB interrupt enable register 1A
0: USB interrupt status register 1B and USB interrupt enable register 1B
6
0 Select ECP-host send-command event. 0: /INT0 1: /INT1
5
0 Select EPP read address E4h event. 0: /INT0. 1: /INT1
4
0 Select EPP write address E4h event. 0: /INT0. 1: /INT1
3
0 Select Interrupt for detecting DMA3 TX done. 0: /INT0 ; 1: /INT1
2
0 Select Interrupt for detecting DMA2 TX done. 0: /INT0 ; 1: /INT1
1
0 Select Interrupt for detecting memory overrun. 0: /INT0 ; 1: /INT1
0
0 Select Interrupt for all USB events. 0: /INT0 ; 1: /INT1
Device Flag Register
CPU Read/Write
Address: FFB1H
Bit Reset Description
7 – 0 - When write: The CPU written data will be latched in buffer, and can be read from
EPP Host with E4h address. The default value is 8’h00
When read: The data comes from EPP Host port E4h (Host Access Device Flag
Register)
DMA3 Byte Count Auto-Reload Control Register
CPU Read/Write
Address: FFB2H
Bit
7–5
4
3
2
1
Reset Description
- Reserved
0 Enable DMA counting value to be read. 0/1: disable/enable
0 Flush USB TX prefetch-buffer. 0/1: disable/enable
0 Force USB TX to be stopped. 0/1 : normal / stop
0 Load TX packet count automatically when packet counter reaches zero (for USB)
When this bit is set, USB TX data is always enabled until this bit is cleared by CPU.
0/1:disable /enable
0
0 Load DMA3 byte count automatically when counter reaches zero (for EPP)
When this bit is enabled, DMA3 is not disabled by hardware, it must be cleared by
firmware. 0/1:disable /enable
USB Received Byte Count Low Register
CPU Read/Write
Address: FFB3H
Bits Reset
Description
47
 

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