GT-6816 View Datasheet(PDF) - Unspecified

Part Name

Description

View to exact match

GT-6816

SCANNER Chips

Unspecified 

GT-6816

DMA2 valid byte count low register

CPU Read/Write

Address: FF89H

Bit Reset Description

7:0 8’b0 DMA2 valid byte count low byte

Note:

These two registers record the valid byte count left in M2. This counter will be increment

when DMA2 transfer occurs, and decrement when DMA3 transfer has been issued.

Before starting scan first line, CPU has to write ‘0’ to clear contents of these two

registers. In normal scanning image process, CPU writes to these two registers are not

recommended.

DMA configuration register

CPU Read/Write

Address: FF8AH

Bit Reset Description

AFE data valid phase

This phase defines the AFE data valid phase referenced to 6-bit dot clock

7:2 6’b0

counter of Timing Generator. This phase can be modified to fit the

optimized quality of AFE output data .

Reset DMA2 FIFO

0 = normal operation

1

1’b0

1 = reset DMA2 FIFO.

Always return ‘0’ when CPU read this bit.

Select external memory

The external memory is now supported to 64K bytes SRAM.

** Entering suspend mode:

0

1’b0

1. Writing expected output data to M2. (CPU cycle)

2. Suspend M2

3. Pin PMDx will output the previous write data to avoid floating output.

DMA2 transfer count high byte register

CPU Read/Write

Address: FF8BH

Bit Reset Description

7:0 8’b0 DMA2 transfer count high byte

DMA2 transfer count low byte register

32

Share Link: