GT-6816
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXA0 control signal falling phase
CPU Read/Write
Address: FF3DH
Bit Reset Description
7:0 2’b0 Reserved
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXA1 control signal rising phase
CPU Read/Write
Address: FF3EH
Bit Reset Description
Polarity
7
1’b0 0 = normal operation
1 = invert MUXA1 output signal
Enable
6
1’b0 0 = disable MUXA1 output
1 = enable MUXA1 output
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXA1 control signal falling phase
CPU Read/Write
Address: FF3FH
Bit Reset Description
7:0 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel counter
AFE MUXB0 control signal rising phase
CPU Read/Write
Address: FF40H
Bit Reset Description
Polarity
7
1’b0 0 = normal operation
1 = invert MUXB0 output signal
Enable
6
1’b0 0 = disable MUXB0 output
1 = enable MUXB0 output
5:0 6’b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXB0 control signal falling phase
CPU Read/Write
Address: FF41H
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