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GT-6816 View Datasheet(PDF) - Unspecified

Part Name
Description
View to exact match
GT-6816
ETC
Unspecified ETC
GT-6816 Datasheet PDF : 63 Pages
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GT-6816
Bit Reset Description
CLAMP0 enable
7
1’b0 0 = CLAMP0 output disable
1 = CLAMP0 output enable
CCLP0 enable
6
1’b0 0 = CCLP0 output disable
1 = CCLP0 output enable
5:0 6’b0 Define rising phase referenced to 6-bits pixel clock counter
AFE CCLP0 control signal falling phase
CPU Read/Write
Address: FF21H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel counter
AFE CLAMP1 control signal rising phase
CPU Read/Write
Address: FF22H
Bit Reset Description
7:0 8’b0 Define rising phase referenced to 16-bits counter
AFE CLAMP1 control signal falling phase
CPU Read/Write
Address: FF23H
Bit Reset Description
7:0 8’b0 Define falling phase referenced to 16-bits counter
Note:
These two registers define the rising and falling phase of CLAMP1 control signal, and
only available on the first 256 cycles of 16-bits counter. CLAMP1 output ‘0’ when
16-bits counter exceeds 256 cycle.
AFE CCLP1 control signal rising phase
CPU Read/Write
Address: FF24H
Bit Reset Description
CLAMP1 enable
1’b0 0 = CLAMP1 output disable
1 = CLAMP1 output enable
CCLP1 enable
6
1’b0 0 = CCLP1 output disable
1 = CCLP1 output enable
19
 

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