EC5575E2-HG View Datasheet(PDF) - Unspecified
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EC5575
14+1 Channel Voltage Buffers for TFT LCD
PDmax = Maximum Power Dissipation in the Package. while does not draw any DC load current or reduce
the gain.
The maximum power dissipation actually produced by
an IC is the total quiescent supply current times the
total power supply voltage, plus the power in the IC
due to the loads, or:
PDmax =∑i[VS * ISmax + (VS+ – VO) * IL]
When sourcing, and
PDmax = ∑i[VS * ISmax + (VO – VS-) * IL]
When sinking.
Where:
i = 1 to 4
VS = Total Supply Voltage
ISmax = Maximum Supply Current Per Amplifier
VO = Maximum Output Voltage of the Application
IL= Load current
RL= Load Resistance = (VS+ – VO)/IL = (VO – VS-)/ IL
A calculation for RL to prevent device from overheat
can be easily solved by setting the two PDmax
equations equal to each other.
Power Supply Bypassing and Printed Circuit
Board Layout
With high phase margin, the EC5575 performs stable
gain at high frequency. Like any high-frequency
device, good layout of the printed circuit board usually
comes with optimum performance. Ground plane
construction is highly recommended, lead lengths
should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, where
the VS- pin is connected to ground, a 0.1 µF ceramic
capacitor should be placed from VS+ pin to VS- pin as
a bypassing capacitor. A 4.7µF tantalum capacitor
should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be
used for multiple devices. This same capacitor
combination should be placed at each supply pin to
ground if split supplies are to be used.
Pin
Count
Θja
Θjc
(oC/W) (C/W)
TQFP-48
67
31 Normal
TQFP-48
31
15 EXPOSED PAD
1V
Driving Capacitive Loads
The EC5575 is designed to drive a wide range of
capacitive loads. In addition, the output current
handling capability of the device allows for good
slewing characteristics even with large capacitive
loads. The combination of these features make the
EC5575 ideally for applications such as TFT LCD
panel grayscale reference voltage buffers, ADC input
amplifiers, etc.
As load capacitance increases, however, the -3dB
bandwidth of the device will decrease and the
peaking increase. The amplifiers drive 10pF loads in
parallel with10KΩ. with just 1.5dB of peaking, and
100pF with 6.4dB of peaking. If less peaking is
desired in these applications, a small series resistor
(usually between 5Ωand 50Ω) can be placed in
series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing
peaking is to add a "snubber" circuit at the output. A
snubber is a shunt load consisting of a resistor in
series with a capacitor. Values of 150Ω and 10nF
are typical. The advantage of a snubber is that it
improves the settling and overshooting performance
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 12
2007/09/12
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