Figure 17.13 Alternate CE# Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tWHWH1 or 2
A0 for program PD for program
55 for erase
30 for sector erase
10 for chip erase
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
18. Erase and Programming Performance
Typ (Note 1)
Max (Note 2)
Sector Erase Time
Chip Erase Time
Excludes 00h programming
prior to erasure (Note 4)
Byte Programming Time
Word Programming Time
Chip Programming Time Byte Mode
Excludes system level
overhead (Note 5)
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10.1
on page 30 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
S29AL016D_00_A8 February 27, 2009