Data Sheet
Addresses
CE#
Figure 17.6 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tWC
2AAh
tAS
SA
555h for chip erase
tAH
Read Status Data
VA
VA
OE#
WE#
Data
tCH
tWP
tCS
tWPH
tDS
tDH
55h
RY/BY#
VCC
tVCS
30h
10 for Chip Erase
tBUSY
tWHWH2
In
Progress
Complete
tRB
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 31).
2. Illustration shows device in word mode.
Addresses
CE#
OE#
WE#
Data
Figure 17.7 Back to Back Read/Write Cycle Timing
tWC
PA
tAH
tRC
PA
tACC
tCE
PA
tCPH
tWDH
tWP
tSR/W
tDS
tDH
Valid In
tOE
tGHWL
tDF
tOH
Valid Out
Valid
In
PA
tCP
Valid
Out
44
S29AL016D
S29AL016D_00_A8 February 27, 2009