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S29AL016 View Datasheet(PDF) - Spansion Inc.

Part Name
Description
MFG CO.
S29AL016 Datasheet PDF : 55 Pages
Data Sheet
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 7.1 S29AL016D Device Bus Operations
DQ8–DQ15
Read
Write
Operation
Standby
CE# OE# WE# RESET#
L
LH
H
L
HL
H
VCC ±
0.3 V
X
X
VCC ±
0.3 V
Addresses
(Note 1)
AIN
AIN
X
DQ0–
DQ7
DOUT
DIN
High-Z
BYTE#
= VIH
DOUT
DIN
High-Z
BYTE#
= VIL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z
Output Disable
L
HH
H
X
High-Z High-Z
High-Z
Reset
X
XX
L
X
High-Z High-Z
High-Z
Sector Address,
Sector Protect (Note 2)
L
HL
VID
A6 = L, A1 = H,
DIN
X
X
A0 = L
Sector Address,
Sector Unprotect (Note 2)
L
HL
VID
A6 = H, A1 = H,
DIN
X
X
A0 = L
Temporary Sector
Unprotect
X
XX
VID
AIN
DIN
DIN
High-Z
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 ± 0.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/
Unprotection on page 19.
7.1 Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
14
S29AL016D
S29AL016D_00_A8 February 27, 2009
 

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