TDA8359 View Datasheet(PDF) - Unspecified

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Description

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TDA8359

Full bridge vertical deflection output circuit in LVDMOS

Unspecified 

Philips Semiconductors

Full bridge vertical deflection output circuit

in LVDMOS

Product specification

TDA8359J

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Flyback switch

Io(peak)

Vloss(FB)

maximum (peak) output current

voltage loss at flyback

t ≤ 1.5 ms

note 11

Io = 1.1 A

Io = 1.6 A

−

−

±1.8 A

−

7.5

8.5

V

−

8

9

V

Guard circuit

VO(grd)

guard output voltage

VO(grd)(max) allowable guard voltage

IO(grd)

output current

IO(grd) = 100 µA

5

6

7

V

maximum leakage current −

−

18

V

IL(max) = 10 µA

VO(grd) = 0 V; not active

−

−

10

µA

VO(grd) = 4.5 V; active

1

−

2.5

mA

Notes

1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and VFB at the first part of the flyback.

2. Allowable input range for both inputs: VI(bias) + Vi < 1600 mV and VI(bias) − Vi > 100 mV.

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and

between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and

between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time

parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists

of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,

where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum,

maximum and average voltages respectively. The linearity errors are defined as:

a) LE = -V----k---V-–---a-V--v--gk----+---1- × 100 % (adjacent blocks)

b) LE = V-----m----a-V--x--a-–--v---gV----m----i--n- × 100 % (non adjacent blocks)

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage

dependent S-distortion in the input stage.

7. Gv(ol) = V--V---F-O--E--U-E---T-D--A-B---–--–---V-V---O-O---U-U---T-T--B-B-

8. Pin FEEDB not connected.

9. Gv = -V----F--V-E---E-I-N--D--A-B---–--–---V-V---I-O-N---BU----T---B-

10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.

11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.

2002 Jan 21

7

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