AD9608BCPZ-105 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9608BCPZ-105

10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Analog Devices 

AD9608

Parameter

Temp Min

Typ

Max

Unit

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode

Full

290

345

400

mV

Output Offset Voltage (VOS), ANSI Mode

Full

1.15

1.25

1.35

V

Differential Output Voltage (VOD), Reduced Swing Mode

Full

160

200

230

mV

Output Offset Voltage (VOS), Reduced Swing Mode

Full

1.15

1.25

1.35

V

1 Pull up.

2 Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 4.

AD9608-105

AD9608-125

Parameter

Temp Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

1000

1000

Conversion Rate1

DCS Enabled

Full

20

105

20

125

DCS Disabled

Full

10

105

10

125

CLK Period—Divide-by-1 Mode (tCLK)

Full

9.52

8

CLK Pulse Width High (tCH)

Full

4.76

4

Aperture Delay (tA)

Full

1.0

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.07

0.07

DATA OUTPUT PARAMETERS

CMOS Mode

CMOS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD)

DCO Propagation Delay (tDCO)2

Full

1.8

2.9

4.4

1.8

2.9

4.4

Full

2.0

3.1

4.4

2.0

3.1

4.4

DCO to Data Skew (tSKEW)

Full

−1.2

−0.1

+1.0

−1.2

−0.1

+1.0

LVDS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD)

Full

2.4

2.4

DCO Propagation Delay (tDCO)2

Full

4.4

4.4

DCO to Data Skew (tSKEW)

Full

−0.1

+0.2

+0.5

−0.1

+0.2

+0.5

CMOS Mode Pipeline Delay (Latency)

Full

16

16

LVDS Mode Pipeline Delay (Latency)

Full

Channel A/Channel B

16/16.5

16/16.5

Wake-Up Time (Power-Down)3

Full

350

350

Wake-Up Time (Standby)

Full

250

250

Out-of-Range Recovery Time

Full

2

2

Unit

MHz

MSPS

MSPS

ns

ns

ns

ps rms

ns

ns

ns

ns

ns

ns

Cycles

Cycles

μs

ns

Cycles

1 Conversion rate is the clock rate after the divider.

2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18).

3 Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. 0 | Page 7 of 40

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