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8S003F3 View Datasheet(PDF) - STMicroelectronics

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8S003F3 Datasheet PDF : 103 Pages
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STM8S003F3 STM8S003K3
3
Block diagram
Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
Reset
Single wire
debug interface
400 Kbit/s
8 Mbit/s
LIN master
SPI emul.
up to 5
channels
1/2/4 kHz beep
Reset block
Reset
POR
BOR
Clock controller
Detector
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock to peripherals and core
STM8 core
Debug/SWIM
Window WDG
Independent WDG
8 Kbyte
program Flash
I2C
SPI
UART2
ADC1
Beeper
128 byte
data EEPROM
1 Kbyte RAM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timer (TIM2)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
3 CAPCOM
channels
8-bit basic timer
(TIM4)
AWU timer
DocID018576 Rev 6
11/103
29
 

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