AD8571ARMZ View Datasheet(PDF) - Analog Devices
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AD8571ARMZ Datasheet PDF : 24 Pages
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AD8571/AD8572/AD8574
Therefore,
VOS, EFF
≈ VOSA + VOSB
BA
(14)
Thus, the offset voltages of both the primary and nulling
amplifiers are reduced by the gain factor BA, which takes a typical
input offset voltage from several millivolts down to an effective
input offset voltage of submicrovolts. This autocorrection scheme
makes the AD857x family of amplifiers extremely precise.
HIGH GAIN, CMRR, AND PSRR
Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in
its input common-mode or power supply voltages. As shown in
the Amplification Phase section, the autocorrection architecture
of the AD857x allows it to effectively minimize offset voltages.
The technique also corrects for offset errors caused by common-
mode voltage swings and power supply variations, which results
in superb CMRR and PSRR figures in excess of 130 dB. Because
the autocorrection occurs continuously, these figures can be
maintained across the temperature range of the device (−40°C
to +125°C).
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around
the amplifier inputs further reduces leakage currents. Figure 52
shows how the guard ring should be configured, and Figure 53
shows the top view of how a surface-mount layout can be
arranged. The guard ring does not need to be a specific width,
but it should form a continuous loop around both inputs. By
setting the guard ring voltage equal to the voltage at the non-
inverting input, parasitic capacitance is minimized as well. For
further reduction of leakage currents, components can be mounted
to the PCB using Teflon® standoff insulators.
VOUT
VIN
AD8572
VIN
VOUT
AD8572
VIN
VOUT
AD8572
Figure 52. Guard Ring Layout and Connections to
Reduce PCB Leakage Currents
R1
VIN1
V+
R2
AD8572
R2
R1
VIN2
GUARD
RING
VREF
GUARD
RING
VREF
V–
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the junction temperature. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
view of the thermal voltage error sources. When the temperature
of the PCB at one end of the component (TA1) differs from the
temperature at the other end (TA2), the Seebeck voltages are not
equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
that both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on the
circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and also
reduces EMI noise pickup.
COMPONENT
LEAD
VSC1 +
–
VTS1
+
–
SURFACE MOUNT
COMPONENT
SOLDER
VSC2
+
–
VTS2
+
–
PC BOARD
TA1
COPPER
TRACE
TA2
IF TA1 ≠ TA2, THEN
VTS1 + VSC1 ≠ VTS2 + VSC2
Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
RF
R1
VIN
RS = R1
VOUT
AD8571/AD8572/
AD8574
AV = 1 + (RF /R1)
RS SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors
Rev. E | Page 16 of 24
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