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A6402 View Datasheet(PDF) - Altera Corporation

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A6402 Datasheet PDF : 8 Pages
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a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
s Parity generator—The parity generator calculates the
appropriate parity value depending on the epe input (even or
odd parity) and the cls inputs (data word length).
s Transmitter multiplexer—The transmitter multiplexer selects a
single-bit data value and drives the tro output. Inputs to the
transmitter multiplexer include the start bit, all eight bits from
the transmitter register, the parity bit, and a stop or idle bit.
Receiver
The receiver consists of the following elements:
s Receiver control—The receiver control contains three
interconnected state machines. The first state machine performs
a divide-by-16 operation on the rrc clock to determine when to
sample the rri serial input. The second state machine detects
the high-to-low transition on rri, determines if a valid start bit
has been received, transfers data from the receiver register to the
receiver buffer register, and generates the status signals dr and
oe. The third state machine loads the individual bits of the
receiver register and the fe and pe outputs.
s Receiver register—The receiver register loads the number of data
bits determined by the cls inputs. If the data word is less than
eight bits, the data is right-justified with the MSBs filled with
logic lows. When the stop bit is detected, the receiver register
transfers its contents to the receiver buffer register.
s Parity check—The parity check calculates the parity of the data
word and the parity bit. If an error occurs, the pe output is
asserted. Once asserted, the pe output can only be cleared by
asserting the mr input.
s Stop check—The stop check samples the middle of the first
expected stop bit. If an error occurs, the fe output is asserted.
Once asserted, the fe output can only be cleared by asserting
the mr input.
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