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ADV601LC View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADV601LC
ADI
Analog Devices ADI
ADV601LC Datasheet PDF : 44 Pages
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ADV601LC
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV601LC’s Compressed Data register.
Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt
Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect
Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the RD or WR
signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.
Table XXIX. Host (Compressed Data) Read Timing Parameters
Parameter
tRD_CD_RDC
tRD_CD_PWA
tRD_CD_PWD
tADR_CD_RDS
tADR_CD_RDH
tDATA_CD_RDD
tDATA_CD_RDOH
tACK_CD_RDD
tACK_CD_RDOH
Description
RD Signal, Compressed Data Direct Register, Read Cycle Time
RD Signal, Compressed Data Direct Register, Pulsewidth Asserted
RD Signal, Compressed Data Direct Register, Pulsewidth Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK Signal, Compressed Data Direct Register, Read Delay
ACK Signal, Compressed Data Direct Register, Read Output Hold
Min Max Unit
28
N/A ns
10
N/A ns
10
N/A ns
2
N/A ns
2
N/A ns
N/A 10
ns
18
N/A ns
N/A 18
ns
9
N/A ns
(I) RD
(I) ADR, BE, CS
(O) DATA
(O) ACK
tRD_CD_RDC
tRD_CD_PWA
VALID
t ADR_CD_RDS
VALID
tRD_CD_PWD
t ADR_CD_RDH
t DATA_CD_RDOH
VALID
VALID
t DATA_CD_RDD
t ACK_CD_RDOH
t ACK_CD_RDD
Figure 30. Host (Compressed Data) Read Transfer Timing
–40–
REV. 0
 

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