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MC74HC4060 View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
View to exact match
MC74HC4060
Motorola
Motorola => Freescale Motorola
MC74HC4060 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
MC54/74HC4060
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
VCC
V
v v – 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trec
Minimum Recovery Time, Reset Inactive to Osc In*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 2)
2.0
100
125
150
ns
4.5
20
25
30
6.0
17
21
26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw
Minimum Pulse Width, Osc In
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
2.0
80
4.5
16
6.0
14
100
120
ns
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw
Minimum Pulse Width, Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 2)
2.0
80
4.5
16
6.0
14
100
120
ns
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tr, tf
Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
2.0
1000
1000
1000
ns
4.5
500
500
500
6.0
400
400
400
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* Osc In driven with external clock.
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state (forcing all Q out-
puts low) and disables the oscillator.
OUTPUTS
Q4 – Q10, Q12 – Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3)
Active–high outputs. Each QN output divides the oscillator
frequency by 2N. The user should note that Q1, Q2, Q3, and
Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 10, 9)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator.
(See Figures 4 and 5). When Osc In is being driven with an
external clock source, Osc Out 1 and Osc Out 2 must be left
open circuited. With the crystal oscillator configuration in Fig-
ure 6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tf
tr
90%
VCC
OSC IN
50%
10%
GND
tw
1/fmax
tPLH
tPHL
90%
Q1 50%
10%
tTLH
tTHL
Figure 1.
tw
VCC
RESET
50%
GND
tPHL
Q
CLOCK
50%
trec
VCC
50%
GND
Figure 2.
TEST POINT
QN 50%
QN + 1
tPLH
50%
VCC
GND
tPHL
Figure 3.
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
 

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