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MC14020 View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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MC14020
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14020 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MC14020B
14-Bit Binary Counter
The MC14020B 14stage binary counter is constructed with MOS
PChannel and NChannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripplecarry binary counter. The device
advances the count on the negativegoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencydividing circuits.
Features
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line
PinforPin Replacement for CD4020B
These are PbFree Devices
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
0.5 to +18.0
V
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8Second Soldering)
55 to +125
°C
65 to +150
°C
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16 16
P SUFFIX
CASE 648
1
MC14020BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
16
14020BG
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
14
020B
ALYWG
G
1
SOEIAJ16
F SUFFIX
CASE 966
16
MC14020B
ALYWG
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
1
October, 2009 Rev. 6
Publication Order Number:
MC14020B/D
 

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