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AD2S83(1998) View Datasheet(PDF) - Analog Devices

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AD2S83 Datasheet PDF : 19 Pages
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AD2S83–SPECIFICATIONS (؎VS = ؎12 V dc ؎ 5%; VL = +5 V dc ؎ 10%; TA = –40؇C to +85؇C)
Parameter
SIGNAL INPUTS (SIN, COS)
Frequency1
Voltage Level
Input Bias Current
Input Impedance
REFERENCE INPUT (REF)
Frequency
Voltage Level
Input Bias Current
Input Impedance
PERFORMANCE
Repeatability
Allowable Phase Shift
Max Tracking Rate
Bandwidth
ACCURACY
Angular Accuracy
Monotonicity
Missing Codes (16-Bit Resolution)
VELOCITY SIGNAL
LINEARITY2, 3, 4
AD2S83AP
0 kHz–500 kHz
0.5 MHz–1 MHz
AD2S83IP
0 kHz–500 kHz
0.5 MHz–1 MHz
Reversion Error
AD2S83AP
AD2S83IP
DC Zero Offset5
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
INPUT/OUTPUT PROTECTION
Analog Inputs
Analog Outputs
DIGITAL POSITION
Resolution
Output Format
Load
INHIBIT6
Sense
Time to Stable Data
ENABLE6
ENABLE6/Disable Time
BYTE SELECT6
Sense
Logic HI
Logic LO
Time to Data Available
SHORT CYCLE INPUTS
SC1 SC2
00
01
10
11
Conditions
(Signals to Reference)
10 Bits
12 Bits
14 Bits
16 Bits
User Selectable
A, I
Guaranteed Monotonic
A, I
Min
0
1.8
1.0
0
1.0
1.0
–10
1040
260
65
16.25
AD2S83
Typ
2.0
60
Max
20,000
2.2
150
20,000
8.0
60
150
1
+10
؎8 +1 LSB
4
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1 mA Load
±8
Mean Value
Overvoltage Protection
Short Circuit O/P Protection
± 5.6
10, 12, 14, and 16
Bidirectional Natural Binary
Logic LO to INHIBIT
240
Logic LO Enables Position Output
Logic HI Outputs in High
Impedance State
35
MS Byte DB1–DB8
LS Byte DB1–DB8
60
Internally Pulled High via
100 kto +VS
10-Bit Resolution
12-Bit Resolution
14-Bit Resolution
16-Bit Resolution
± 0.15
± 0.25
± 0.25
± 0.25
± 0.5
± 1.0
±3
± 1.5
±8
±8
؎0.25
؎1.0
؎0.5
؎1.0
؎1.0
؎1.5
؎3
1.0
± 10.4
3
390
490
110
140
–2–
Units
Hz
V rms
nA
M
Hz
V pk
nA
M
LSB
Degree
rps
rps
rps
rps
arc min
Codes
% FSR
% FSR
% FSR
% FSR
% O/P
% O/P
mV
% FSR
V
% rms O/P
V
mA
Bits
LSTTL
ns
ns
ns
REV. D
 

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