FW323-05 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

View to exact match

FW323-05

1394A PCI PHY/Link Open Host Controller Interface

Agere -> LSI Corporation 

Data Sheet, Rev. 2

October 2001

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Pin

Symbol*

Type

Description

101

TPBIAS2

102

VSSA

103

VSSA

104

VDDA

105

TPB1–

106

TPB1+

107

TPA1–

108

TPA1+

109

TPBIAS1

110

TPB0–

111

TPB0+

112

TPA0–

113

TPA0+

114

TPBIAS0

115

VSSA

116

VDDA

Analog I/O

—

—

—

Analog I/O

Analog I/O

Analog I/O

Analog I/O

Analog I/O

Analog I/O

—

—

Port 2, Twisted-Pair Bias. TPBIAS2 provides the

1.86 V nominal bias voltage needed for proper opera-

tion of the twisted-pair cable drivers and receivers and

for sending a valid cable connection signal to the

remote nodes.

Analog Circuit Ground. All VSSA signals should be

tied together to a low-impedance ground plane.

Analog Circuit Ground. All VSSA signals should be

tied together to a low-impedance ground plane.

Analog Circuit Ground. VDDA supplies power to the

analog portion of the device.

Port 1, Port Cable Pair B. TPB1± is the port B connec-

tion to the twisted-pair cable. Board traces from each

pair of positive and negative differential signal pins

should be kept matched and as short as possible to the

external load resistors and to the cable connector.

Port 1, Port Cable Pair A. TPA1± is the port A connec-

tion to the twisted-pair cable. Board traces from each

pair of positive and negative differential signal pins

should be kept matched and as short as possible to the

external load resistors and to the cable connector.

Port 1, Twisted-Pair Bias. TPBIAS1 provides the

1.86 V nominal bias voltage needed for proper opera-

tion of the twisted-pair cable drivers and receivers and

for sending a valid cable connection signal to the

remote nodes.

Port 0, Port Cable Pair B. TPB0± is the port B connec-

tion to the twisted-pair cable. Board traces from each

pair of positive and negative differential signal pins

should be kept matched and as short as possible to the

external load resistors and to the cable connector.

Port 0, Port Cable Pair A. TPA0± is the port A connec-

tion to the twisted-pair cable. Board traces from each

pair of positive and negative differential signal pins

should be kept matched and as short as possible to the

external load resistors and to the cable connector.

Port 0, Twisted-Pair Bias. TPBIAS0 provides the

1.86 V nominal bias voltage needed for proper opera-

tion of the twisted-pair cable drivers and receivers and

for sending a valid cable connection signal to the

remote nodes.

Analog Circuit Ground. All VSSA signals should be

tied together to a low-impedance ground plane.

Analog Circuit Power. VDDA supplies power to the

analog portion of the device.

* Active-low signals within this document are indicated by an N following the symbol names.

Agere Systems Inc.

17

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