|FW32305||1394A PCI PHY/Link Open Host Controller Interface|
Agere -> LSI Corporation
|FW32305 Datasheet PDF : 152 Pages |
Data Sheet, Rev. 2
1394A PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
regardless of whether a cable is connected to port or
not connected to a port. For those applications, when
FW323 is used with one or more of the ports not
brought out to a connector, those unused ports may be
left unconnected without normal termination. When a
port does not have a cable connected, internal
connect-detect circuitry will keep the port in a
Note: All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY core configuration packets (see Section
126.96.36.199 of IEEE 1394-1995 standard) or by using
two bus resets, which resets the gap counts to
the maximum level (3Fh).
The internal link power status (LPS) signal works with
the internal LinkOn signal to manage the LLC power
usage of the node. The LPS signal indicates that the
LLC of the node is powered up or down. If LPS is
inactive for more than 1.2 µs and less than 25 µs, the
internal PHY/link interface is reset.
If LPS is inactive for greater than 25 µs, the PHY will
disable the internal PHY/link interface to save power.
The FW323 continues its repeater function. If the PHY
then receives a link-on packet, the internal LinkOn sig-
nal is activated to output a 6.114 MHz signal, which can
be used by the LLC to power itself up. Once the LLC is
powered up, the internal LPS signal communicates this
to the PHY and the internal PHY/link interface is
enabled. Internal LinkOn signal is turned off when LCtrl
bit is set.
Three of the signals are used to set up various test
conditions used in manufacturing. These signals (SE,
SM, and PTEST) should be connected to VSS for
Agere Systems Inc.
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