1340FBPC View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

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1340FBPC

1340-Type Lightwave Receiver

Agere -> LSI Corporation 

1340-Type Lightwave Receiver

Data Sheet

January 2000

Data and Flag Outputs (continued)

The FLAG and FLAG outputs of the OC-3/STM-1

155 Mbits/s version of the 1340 receiver are PECL

logic levels driven by open emitter transistors with the

same characteristics as the data outputs. These out-

puts must be properly terminated in order to obtain the

correct logic levels. Since the FLAG function is basi-

cally a dc switch that indicates the loss of optical input

signal, it can be interfaced to much slower TTL or

CMOS logic circuits.

The circuit shown in Figure 2 provides one example of

how to create a TTL logic output from the PECL FLAG

output signal. The outputs of the LT1016 are TTL-com-

patible and provide both true and inverted logic levels.

The Q output of this circuit will be a TTL high (>2.5 V)

when the 1340 is receiving an optical signal greater

than the FLAG switching threshold and will be a TTL

low (<0.4 V) whenever the optical signal is absent or is

below the FLAG switching threshold. The FLAG and

FLAG outputs of the OC-12/STM-4 and 1.25 Gbits/s

receivers are 5 V TTL logic level compatible. The FLAG

output is provided directly by the comparator IC. How-

ever, the FLAG output is derived from the FLAG output

through an inverter. Excessive loading of the FLAG out-

put can cause the FLAG output to malfunction.

+5 V

11

1340

RX

12

FLAG

14

FLAG

10 k•

+5 V

+

Q

LT1016*

–

Q

10 k•

TTL (TRUE)

TTL (INVERTED)

* Part available from Linear Technology Corporation of Milpitas, CA 95035.

Figure 2. Converting PECL FLAG Outputs to TTL

1-800(C).a

4

Agere Systems Inc.

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