1340CMPC View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

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1340CMPC

1340-Type Lightwave Receiver

Agere -> LSI Corporation 

Data Sheet

January 2000

1340-Type Lightwave Receiver

Description (continued)

To help ensure high product reliability and customer

satisfaction, Agere is committed to an intensive quality

program that starts in the design phase and proceeds

through the manufacturing and shipping process. Opto-

electronics subsystems are qualified to Agere internal

standards using MIL-STD-883 test methods and pro-

cedures and sampling techniques consistent with Tel-

cordia Technologies requirements. The 1340 receiver

qualification program meets the intent of Telcordia

Technologies TR-NWT-000468 andTA-TSY-000983.

Application Information

Noise that couples into the receiver through the power

supply pins can also degrade device performance. The

application schematics, Figures 3—5, show recom-

mended power supply filtering that helps minimize

noise coupling into the receiver. The bypass capacitors

should be high-quality ceramic devices rated for RF

applications. They should be surface-mount compo-

nents placed as close as possible to the receiver power

supply pins. The ferrite bead should have as high an

impedance as possible in the frequency range that is

most likely to cause problems. This will vary for each

application and is dependent on the signaling frequen-

cies present on the application circuit card. Surface-

mount, high-impedance beads are available from sev-

eral manufacturers.

The 1340 receiver is a highly sensitive fiber-optic

receiver. Although the data outputs are digital logic lev-

els (PECL), the device should be thought of as an ana-

log component. When laying out the printed-wiring

board (PWB), the 1340 receiver should be given the

same type of consideration one would give to a sensi-

tive analog component.

At a minimum, a double-sided printed-wiring board with

a large component-side ground plane beneath the

receiver must be used. In applications that include

many other high-speed devices, a multilayer PWB is

highly recommended. This permits the placement of

power and ground connections on separate layers,

which helps minimize the coupling of unwanted signal

noise into the power supplies of the receiver.

Layout Considerations

A fiber-optic receiver employs a very high-gain, wide-

bandwidth transimpedance amplifier. The amplifier

detects and amplifies signals that are only tens of nA in

amplitude. Any unwanted signal currents that couple

into the receiver circuitry cause a decrease in the

receiver’s sensitivity and can also degrade the perfor-

mance of the receiver’s loss of signal (FLAG) circuit.

To minimize the coupling of unwanted noise into the

receiver, route high-level, high-speed signals such as

transmitter inputs and clock lines as far away as possi-

ble from the receiver pins. If this is not possible, then

the PWB layout engineer should consider interleaving

the receiver signal and flag traces with ground traces in

order to provide the required isolation.

Data and Flag Outputs

The data outputs of the 1340 receiver are driven by

open-emitter NPN transistors which have an output

impedance of approximately 7 Ω. Each output can pro-

vide approximately 50 mA maximum output current.

Due to the high switching speeds of ECL outputs,

transmission line design must be used to interconnect

components. To ensure optimum signal fidelity, both

data outputs (DATA and DATA) should be terminated

identically. The signal lines connecting the data outputs

to the next device should be equal in length and should

have matched impedances.

Controlled impedance stripline or microstrip construc-

tion must be used to preserve the quality of the signal

into the next component and to minimize reflections

back into the receiver. Excessive ringing due to reflec-

tions caused by improperly terminated signal lines

makes it difficult for the component receiving these sig-

nals to decipher the proper logic levels and may cause

transitions to occur where none were intended. Also, by

minimizing high frequency ringing due to reflections

caused by improperly designed and terminated signal

lines, possible EMI problems can be avoided. The

applications sections in the Signetics*ECL 10K/100K

Data Manual or the National Semiconductor † ECL

Logic Databook and Design Guide provide excellent

design information on ECL interfacing.

* Signetics is a registered trademark of Signetics Corp.

† National Semiconductor is a registered trademark of National

Semiconductor Corporation.

Agere Systems Inc.

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