|CXK591000YM-55LL||131,072-word ×9-bit High Speed CMOS Static RAM|
|CXK591000YM-55LL Datasheet PDF : 13 Pages |
• Write cycle (3) : CE2 control
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the
end of the write cycle.
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