MTV121 View Datasheet(PDF) - Myson Century Inc

Part Name

Description

View to exact match

MTV121

Super On-Screen-Display for LCD Monitor

Myson Century Inc 

MYSON

TECHNOLOGY

MTV121

The vertical display center for full screen display could be figured out according to the information of vertical

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,

is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H

TABLE 2. Repeat line weight of character

CH6 - CH0

CH6,CH5=11

CH6,CH5=10

CH6,CH5=0x

CH4=1

CH3=1

CH2=1

CH1=1

CH0=1

Repeat Line Weight

+18*3

+18*2

+18

+16

+8

+4

+2

+1

Where H = one horizontal line display time

TABLE 3. Repeat line number of character

Repeat Line

Repeat Line #

Weight

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

+1

- - - - - - - -v- - - - - - - - -

+2

- - - -v- - - - - - -v- - - - -

+4

- -v- - -v- - -v- - -v- - -

+8

-v-v-v-v-v-v-v-v- -

+16

- vvvvvvvvvvvvvvvv -

+17

vvvvvvvvvvvvvvvvv -

+18

vvvvvvvvvvvvvvvvvv

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

character would not be repeated.

3.4 Horizontal display control

The horizontal display control is used to generate control timing for horizontal display based on double char-

acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and

HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-

acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-

lated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P

Where P = 1 XIN pixel display time

3.5 Display & Row control registers

The internal RAM contains display and row control registers. The display registers have 450 locations which

are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register

has its corresponding character address on ADDRESS byte, its corresponding background color, 1 blink bit

and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for

row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen,

only even column characters could be displayed on screen and the odd column characters will be hidden.

6/18

MTV121 Revision 5.0 06/29/1999

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