datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

MTV121N20 View Datasheet(PDF) - Myson Century Inc

Part Name
Description
View to exact match
MTV121N20
Myson
Myson Century Inc Myson
MTV121N20 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MYSON
TECHNOLOGY
MTV121
b7 b6 b5 b4 b3 b2 b1 b0
Column 15
Reserved
This byte is reserved for internal testing.
b7 b6 b5 b4 b3 b2 b1 b0
Column 16 -
-
-
RSPACE
MSBLSB
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
b7
b6
b5
b4
b3
b2
b1
b0
Column 17 OSDEN BSEN SHADOW FAN BLANK WENCLR RAMCLR FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen.
FAN - Enable the fade-in/fade-out function when OSD is turned on from off state or vice verca. The function
roughly takes about one second to fully display the whole menu or to disappear completely.
BLANK - Force the FBKG pin output to high while this bit is set to "1".
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the dis-
playing of characters or windows, otherwise, it outputs only during the displaying of character.
B7
b6
b5
Column 18 TRIC FBKGP PWMCK
b4
DWE
b3
HSP
b2
b1
b0
VSP PWM1 PWM0
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That
is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins
are in high impedance state. The initial value is 0 after power up.
FBKGP - Select the polarity of the output pin FBKG
=1
Positive polarity FBKG output is selected.
=0
Negative polarity FBKG output is selected.
The initial value is 1 after power up.
PWMCK - Select the output options to HTONE/PWMCK pin.
=0
HTONE option is selected.
=1
PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB.
The frequency is selected by (PWM1, PWM0) shown as Table 5.
10/18
MTV121 Revision 5.0 06/29/1999
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]