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TDA9605H/N1 View Datasheet(PDF) - Philips Electronics

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TDA9605H/N1 Datasheet PDF : 52 Pages
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Philips Semiconductors
Audio processor with head amplifier for VHS hi-fi
Product specification
TDA9605H
7 I2C-BUS PROTOCOL
7.1 Addresses and data bytes
Full control of the TDA9605H is accomplished via the 2-wire I2C-bus. Bus speeds up to 400 kbits/s can be used in
accordance with the I2C-bus fast-mode specification.
Seven data byte registers are available for programming the device (write mode) and one data byte register is available
for reading data from the device (read mode). The registers are addressable via eight subaddresses. Automatic
subaddress incrementing enables writing of successive data bytes in one transmission.
During power-up, the data byte registers and auto-calibration registers are reset to a default state by the use of a
Power-On Reset (POR) circuit. The reset signal is derived from an internally generated voltage supplied by VCC.
Table 6 Addresses and POR state bits
NAME
ADDRESS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Write mode
Slave byte
Subaddress byte
Control byte
POR state
Select byte
POR state
Input byte
POR state
Output byte
POR state
Left volume byte
POR state
Right volume byte
POR state
Volume byte
Power byte
POR state
B8H
1
0
1
1
1
0
0
0
00H to 07H;
0
0
0
0
0
0 or 1 0 or 1 0 or 1
note 1
subaddress 00H AFM DOC SHH DETH NTSC HAC2 HAC1 HAC0
1
0
0
0
1
0
0
0
subaddress 01H DOS1 DOS0 s5
HRL NIL3 NIL2 NIL1 NIL0
0
0
0(2)
0
0
0
0
0
subaddress 02H i7
IS2
IS1
IS0
NS2 NS1 NS0 i0
0(2)
0
0
0
1
1
1
0(2)
subaddress 03H LOH OSN OSR OSL EOS LOS DOS RFCM
0
0
0
0
0
0
0
1
subaddress 04H l7
VLS VL5 VL4 VL3 VL2 VL1 VL0
0(2)
1
0
0
0
0
0
0
subaddress 05H r7
VRS VR5 VR4 VR3 VR2 VR1 VR0
0(2)
1
0
0
0
0
0
0
subaddress 06H simultaneous loading of the subaddress 04H and subaddress 05H registers
subaddress 07H CALS VCCS TEST PORR HPD MUTE STBP STBA
0
0
0
0
0
1
0
0
Read mode
Slave address byte B9H
Read byte
B9H
1
0
1
1
1
0
0
1
CALR AUTN CALE POR 0(3)
0(3)
0(3)
0(3)
Notes
1. Continuous writing to a single data byte register is possible when subaddresses F0H to F7H (1111 0xxx) are used
instead of 00H to 07H (0000 0xxx). In that case automatic subaddress incrementing is disabled.
2. It is advised to keep the not-used write bits equal to the POR state to accommodate future compatibility.
3. You cannot rely upon the state of the not-used read bits because their state may change during development.
1999 Apr 14
18
 

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