ST10F168-Q6 View Datasheet(PDF) -

ST10F168

16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM

s HIGH PERFORMANCE CPU

– 16-BIT CPU WITH 4-STAGE PIPELINE

– 80ns INSTRUCTION CYCLE TIME AT 25MHz

CPU CLOCK

– 400ns 16 X 16-BIT MULTIPLICATION

– 800ns 32 / 16-BIT DIVISION

– ENHANCED BOOLEAN BIT MANIPULATION

FACILITIES

– ADDITIONAL INSTRUCTIONS TO SUPPORT

HLL AND OPERATING SYSTEMS

– SINGLE-CYCLE CONTEXT SWITCHING SUP-

PORT

s MEMORY ORGANIZATION

– 256K BYTE ON-CHIP FLASH MEMORY

– 10K ERASING / PROGRAMMING CYCLES

– UP TO 16M BYTE LINEAR ADDRESS SPACE

FOR CODE AND DATA (5M BYTE WITH CAN)

– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)

– 6K BYTE ON-CHIP EXTENSION RAM (XRAM)

– 20 YEAR DATA RETENTION TIME

s FAST AND FLEXIBLE BUS

– PROGRAMMABLE EXTERNAL BUS CHARAC-

TE- RISTICS FOR DIFFERENT ADDRESS

RANGES

– 8-BIT OR 16-BIT EXTERNAL DATA BUS

– MULTIPLEXED OR DEMULTIPLEXED EXTER-

NAL ADDRESS / DATA BUSES

– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS

– HOLD-ACKNOWLEDGE BUS ARBITRATION

SUPPORT

s INTERRUPT

– 8-CHANNEL PERIPHERAL EVENT CONTROL-

LER FOR SINGLE CYCLE, INTERRUPT DRIVEN

DATA TRANSFER

– 16-PRIORITY-LEVEL INTERRUPT SYSTEM

WITH 56 SOURCES, SAMPLE-RATE DOWN TO

40ns

s TIMERS

– TWO MULTI-FUNCTIONAL GENERAL PUR-

POSE TIMER UNITS WITH 5 TIMERS

– TWO 16-CHANNEL CAPTURE / COMPARE

UNITS.

s 4-CHANNEL PWM UNIT

s SERIAL CHANNELS

– SYNCHRONOUS / ASYNCHRONOUS SERIAL

CHANNEL

– HIGH-SPEED SYNCHRONOUS CHANNEL

PQFP144 (28 x 28 mm)

(Plastic Quad Flat Pack)

s A/D CONVERTER

– 16-CHANNEL 10-BIT

– 7.76µS CONVERSION TIME

s FAIL-SAFE PROTECTION

– PROGRAMMABLE WATCHDOG TIMER

– OSCILLATOR WATCHDOG

s ON-CHIP CAN 2.0B INTERFACE

s ON-CHIP BOOTSTRAP LOADER

s CLOCK GENERATION

– ON-CHIP PLL

– DIRECT OR PRESCALED CLOCK INPUT.

s UP TO 111 GENERAL PURPOSE I/O LINES

– INDIVIDUALLY PROGRAMMABLE AS INPUT,

OUTPUT OR SPECIAL FUNCTION.

– PROGRAMMABLE THRESHOLD (HYSTERESIS)

s IDLE AND POWER DOWN MODES

s SINGLE VOLTAGE SUPPLY: 5V ±10%

s 144-PIN PQFP PACKAGE

FLASH

CPU Core

PEC

Interrupt controller

RAM

Watchdog

OSC

P.0

P.1

P.4

BRG BRG

P.6

P.5

P.3

P.7

P.8

January 2002

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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