TDAT042G5 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

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TDAT042G5

SONET/SDH 155/622/2488 Mbits/s Data Interfaces

Agere -> LSI Corporation 

Advisory

May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

System Programming (SP)

SP1. Required Provisioning Sequence and Clocks

The core registers must be written prior to provisioning any other registers (1) to establish the internal clock

rates for the device, and (2) because writing to certain core registers resets the remainder of the device. Cer-

tain clocks must be present to read/write registers prior to provisioning the device.

One of the following clocks must be present prior to provisioning to enable register access:

I TxCKP and TxCKN

I MPU clock (microprocessor interface synchronous mode only)

Provisioning must be implemented in the following sequence:

I Core register 0x0010 (mode) must be provisioned first

I Core register 0x0011 (channel [A—D] control) second

I Remainder of the core registers must then be provisioned (order does not matter)

It is recommended, but not required, that the remainder of the device be provisioned in the following order:

I OHP, PT, and DE blocks (order does not matter)

I UT block to turn on the data source to the master and slave

Workaround

Provisioning must be implemented in the following sequence:

I Apply either TxCKP and TxCKN or MPU clock.

I Provision core:

— Mode, register 0x0010

— Channel [A—D] control, register 0x0011

— Remainder of the core

Corrective Action

Not applicable. Use above procedure in provisioning the device.

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