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Z8018110FEC View Datasheet(PDF) - Zilog

Part Name
Description
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Z8018110FEC Datasheet PDF : 0 Pages
Zilog
PERIPHERAL SIGNALS
Z80181
SMART ACCESS CONTROLLER SAC
Pin Name
RXA0, RXA1
Pin Number
70, 74
TXA0, TXA1 69, 72
/RTS0
66
/DCD0
68
/CTS0
67
/CTS1/RXS
77
CKA0//DREQ0 71
CKA1//TEND0 75
/TEND1
80
CKS
78
TXS
76
/DREQ1
79
Input/Output, Tri-State Function
In, Active 1
ASCI Receive Data 0 and 1. These signals are the receive
data to the ASCI channels.
Out, Active 1
ASCI Transmit Data 0 and 1. These signals are the
receive data to the ASCI channels. Transmit data changes
are with respect to the falling edge of the transmit clock.
Out, Active 0
Request to Send 0. This is a programmable modem
control signal for ASCI channel 0.
In, Active 0
Data Carrier Detect 0. This is a programmable modem
control signal for ASCI channel 0.
In, Active 0
Clear To Send 0. This is a programmable modem control
signal for ASCI channel 0.
In, Active 0
Clear To Send 0/Clocked Serial Receive Data. This is a
programmable modem control signal for ASCI channel 0.
Also, this signal becomes receive data for the CSIO
channel under program control. On power-on Reset, this
pin is set as RxS.
I/O, Active 1
Asynchronous Clock0/DMAC0 Request. This pin is the
transmit and receive clock for the Asynchronous channel
0. Also, under program control, this pin is used to request
a DMA transfer from DMA channel 0. DMA0 monitors this
input to determine when an external device is ready for a
read or write operation. On power-on Reset, this pin is
initialized as CKA0.
I/O, Active 1
Asynchronous Clock1/DMAC0 Transfer End. This pin is
the transmit and receive clock for the Asynchronous chan-
nel 1. Also, under program control, this pin becomes
/TEND0 and is asserted during the last write cycle of the
DMA0 operation and is used to indicate the end of the
block transfer. On power-on Reset, this pin initializes
as CKA1.
Out, Active 0
DMAC1 Transfer End. This pin is asserted during the last
write cycle of the DMA1 operation and is used to indicate
the end of the block transfer.
I/O, Active 1
CSIO Clock. This line is the clock for the CSIO channel.
Out, Active 1
CSI/O Tx Data. This line carries the transmit data from the
CSIO channel.
In, Active 0
DMAC1 Request. This pin is used to request a DMA
transfer from DMA channel 1. DMA1 monitors this input to
determine when an external device is ready for a read or
write operation.
2-6
DS971800500
 

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