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LC72720M View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC72720M Single-chip RDS signal-processing system LSI SANYO
SANYO -> Panasonic SANYO
LC72720M Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC72720, 72720M
8. RDS/RBDS (MMBS) selection (1 bit): RM
RM RBDS support
0
None
1
Provided
Initial value: RM = 0
Decoding method
Only RDS data is decoded correctly (Offset word E is not detected.)
RDS and MMBS data is decoded correctly (Offset word E is also detected.)
9. Output pin settings (3 bits): PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins.
PPP
T3
T4
T5
T6
T7
Mode T T T
0 1 2 RDCL RDDA RSFT
ERROR
57K
BE1
CORREC
ARI-ID
BE0
0
000 —
1
100 q
q
q
2
010 q
q
q
q
q
3
110 q
q
q
q
q
4
001 —
q
q
5
101 q
q
q
6
011 q
q
q
q
q
7
111 q
q
q
q
q
—: Open, q, q: Output enabled (q = reverse polarity)
Initial values: PT0 = 1, PT1 = 1, PT2 = 0 (mode 3)
Caution: 1. When PT2 is set to 1, the polarity of the T3 (RDCL), T6 (ERROR/57K), T7 (CORREC/ARI-ID) SYNC, and RDS-ID pins changes to active
high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors to output data.
PT2 = 0
PT2 = 1
Pin T3 (RDCL)
Data (RDDA and RSFT) changes on this pin’s rising edge.
Data (RDDA and RSFT) changes on this pin’s falling edge.
Mode 2 (PT2 = 0)
No SK
SK present
Pin T7 (ARI-ID)
High (1)
Low (0)
Mode 3 (PT2 = 0)
Correction not possible
Errors corrected
No errors
Pin T6 (ERROR)
Low (0)
High (1)
High (1)
Pin T7 (CORREC)
Low (0)
Low (0)
High (1)
Mode 4
Number of error blocks (B)
B=0
1 B 20
20 < B 40
40 < B 48
Pin T6 (BE1)
Low (0)
Low (0)
High (1)
High (1)
Pin T7 (BE0)
Low (0)
High (1)
Low (0)
High (1)
These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values
listed in the table.
No. 5602-9/14
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