M38747MCT-XXXG View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38747MCT-XXXG

Single-chip 8-bit CMOS microcomputer. ROM 61440 bytes, RAM 2048 bytes. Mask ROM version.

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3874 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(3) Arbitrary bit serial I/O mode

Since read and write of the serial I/O3 register are controlled by

the serial I/O3 automatic transfer controller, address 001316 func-

tions as the transfer counter (in byte units).

After the serial I/O3 automatic transfer data pointer and automatic

transfer interval set bits have been set, and an internal synchro-

nous clock selected, serial automatic transfer starts when the

value of the number of transfer bits decremented by 1 is written to

the transfer counter (address 001316), just as in the automatic

transfer serial I/O. When selecting an external synchronous clock,

write the value of the transfer bits decremented by 1 to the trans-

fer counter, then input the transfer clock to SCLK3 after 5 or more

cycles of internal clock φ. The transfer interval after each 8-bit data

transfer must be 5 or more cycles of internal clock φ after the ris-

ing edge of the last bit of the 8-bit data.

When selecting an internal synchronous clock, the automatic

transfer interval can be specified regardless of the contents of the

selected handshake signal.

In this case, when the automatic transfer interval setting is valid

and SBUSY3 output is used there are the transfer interval before

the first data is transmitted/received, as well as after the last data

is transmitted/received just as in the automatic transfer serial I/O

mode. When using SSTB3 output, this transfer interval become 2

cycles longer than the value set for each 8-bit data. In addition,

when using the combined output of SBUSY3 and SSTB3, the trans-

fer interval after completion of transmission/receipt of the last data

become 2 cycles longer than the set value.

When selecting an external synchronous clock, the automatic

transfer interval cannot be specified.

Regardless of internal or external synchronous clock, the auto-

matic transfer data pointer is decremented after each 8-bit data is

received and then written to the auto-transfer RAM. The transfer

counter is decremented with the transfer clock. The serial transfer

status flag is set to “1” by writing to the transfer counter which trig-

gers the start of transmission. After the last data is written to the

automatic transfer RAM, the serial transfer status flag is set to “0”

and a serial I/O3 interrupt request occurs simultaneously.

The write values of the automatic transfer data pointer set bits and

the automatic transfer interval set bits are kept in the latch. As a

transfer counter write occurs, each value is transferred to its corre-

sponding decrement counter.

If the last data does not fill 8 bits, the receive data stored in the se-

rial I/O3 automatic transfer RAM become the closest MSB odd bit

if the transfer direction select bit is set to LSB first, or the closest

LSB odd bit if the transfer direction select bit is set to MSB first.

Automatic transfer

data pointer

5216

Automatic transfer RAM

2FF16

25216

25116

25016

24F16

24E16

Transfer counter

0416

20016

SIN3

Serial I/O3 register

SOUT3

Fig. 38 Automatic transfer serial I/O operation

44

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