M38747MCT-XXXG View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38747MCT-XXXG

Single-chip 8-bit CMOS microcomputer. ROM 61440 bytes, RAM 2048 bytes. Mask ROM version.

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3874 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O

Serial I/O1

Serial I/O can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer (baud rate generator) is

also provided for baud rate generation.

(1) Clock Synchronous Serial I/O1 Mode

Clock synchronous serial I/O1 mode can be selected by setting

the serial I/O1 mode selection bit (b6) of the serial I/O1 control

register to “1”.

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the transmit/receive buffer register (ad-

dress 001816).

Data bus

Address 001816

Receive buffer register (RB)

Serial I/O1 control register

Address 001A16

Receive buffer full flag (RBF)

P44/RXD

Receive shift register

Shift clock

Receive interrupt request (RI)

Clock control circuit

P46/SCLK1

BRG count source selection bit

XIN

1/4

Serial I/O1 synchronous

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator

1/4

Address 001C16

P47/SRDY1

P45/TXD

F/F

Falling-edge detector

Clock control circuit

Shift clock

Transmit shift register shift completion flag (TSC)

Transmit shift register

Transmit interrupt source selection bit

Transmit interrupt request (TI)

Transmit buffer register (TB)

Address 001816

Data bus

Transmit buffer empty flag (TBE)

Serial I/O1 status register

Address 001916

Fig. 26 Block diagram of clock synchronous serial I/O

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial I/O1 output TXD

Serial I/O1 input RXD

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

Receive enable signal SRDY1

Write signal to receive/transmit

buffer register (address 001816)

TBE = 0

TBE = 1

TSC = 0

RBF = 1

TSC = 1

Overrun error (OE)

detection

Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)

or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O1 control register.

2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is

output continuously from the TXD pin.

3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Fig. 27 Operation of clock synchronous serial I/O1 function

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