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M38747MCT-XXXG View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38747MCT-XXXG Datasheet PDF : 92 Pages
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MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 Interrupt vector addresses and priority
Interrupt Sources Priority
Reset (Note 2)
1
INT0
2
INT1
3
Receive bus
4
interrupt source 1
Receive bus
interrupt source 2
Receive bus
interrupt source 3
Transmit bus
5
interrupt source 1
Transmit bus
interrupt source 2
Transmit bus
interrupt source 3
Timer X
6
Timer Y
7
Timer 2
8
Timer 3
9
INT2
10
Serial I/O3
11
interrupt
CNTR0
CNTR1
12
Timer 1
13
INT3
14
INT4
INT5
ADT
15
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
FFF916
FFF816
FFF716
FFF616
FFF516
FFF416
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE716
FFE516
FFE316
FFE616
FFE416
FFE216
FFE116
FFE016
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
When receive bus interrupt
source 1 request bit becomes
“1” from “0”
When receive bus interrupt
source 2 request bit becomes
“1” from “0”
When receive bus interrupt
source 3 request bit becomes
“1” from “0”
When transmit bus interr upt
source 1 request bit becomes
“1” from “0”
When transmit bus interr upt
source 2 request bit becomes
“1” from “0”
When transmit bus interr upt
source 3 request bit becomes
“1” from “0”
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of INT2 input
At completion of serial I/O3 data
transmission/reception
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At detection of either rising or
falling edge of INT5 input
At falling of ADT pin input
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
The condition which the receive
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
The condition which the transmit
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
External interrupt
(active edge selectable)
Valid only when serial I/O3 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid only when ADT interrupt is
selected
External interrupt
(falling valid)
A-D converter
Serial I/O2
interrupt
Key input (key-
16
on wake-up)
FFDF16
FFDE16
At completion of A-D converter
At completion of serial I/O2 data
transmission/reception
At falling of port P20 to P25 (at
input) input logical level AND
Valid only when A-D converter
interrupt is selected
Valid only when serial I/O2 is
selected
External interrupt
(falling valid)
Serial I/O1
receive
Serial I/O1
transmit
BRK instruction
17
FFDD16
FFDC16
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At BRK instruction execution
Valid only when serial I/O1 is
selected
Valid only when serial I/O1 is
selected
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used.
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