M38747MCT-XXXG View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38747MCT-XXXG

Single-chip 8-bit CMOS microcomputer. ROM 61440 bytes, RAM 2048 bytes. Mask ROM version.

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3874 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by 27 sources: 10 external, 16 internal, and 1 soft-

ware.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the

corresponding interrupt request and enable bits are “1” and the in-

terrupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

The interrupt control circuit consists of two types of interrupts: “one

factor/one vector interrupt” and “multiple factors/one vector inter-

rupt”. The configuration is shown in Figure 18.

Interrupt Operation

When an interrupt occurs, the following operations are automati-

cally performed:

1. The contents of the program counter and the processor status

register are pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt

request bit for each vector is cleared. (The corresponding inter-

rupt request bit for each interrupt factor is not cleared.)

3. The interrupt jump destination address of interrupt which has

the highest priority is loaded to the program counter.

Interrupt Factor Determination

The interrupt request bit for each vector of “multiple factors/one

vector interrupt” is set to “1” when the interrupt disable flag (I) is “0”

and one of the factor interrupt enable bits is “1” and the corre-

sponding factor interrupt request bit changes from “0” to “1”. At

this time, if the vector interrupt enable bit is “1”, the interrupt oc-

curs. (Note that the interrupt request bit for each vector and the

factor interrupt request bit are both edge sense.)

When 2 or more interrupt requests of interrupt factors assigned to

one interrupt vector are generated at the same time, confirm the

interrupt request bits for each interrupt factor assigned to the vec-

tor, and process according to the priority.

If the interrupt request bit for the interrupt factor is “1” and the in-

terrupt enable bits for interrupt factor and each vector are both “1”;

for example, when an interrupt of another interrupt factor assigned

to the same vector occurs while an interrupt processing routine is

executed, the interrupt occurs again after returning. Clear the in-

terrupt request bits which are not necessary or which have been

already processed before executing the interrupt flag clear (CLI)

or interrupt processing routine return (RTI) instruction.

The interrupt request bits for each interrupt factor are not cleared

by hardware after an interrupt vector address branching. Clear

these bits by software in the interrupt processing routine. Use the

LDM, STA, etc. instructions to do it. Do not use the read- modify-

write instruction; for example, the CLB.

s Notes

When the active edge of an external interrupt (INT0–INT5, CNTR0,

CNTR1) is set, the corresponding interrupt request bit may also be

set. Therefore, take following sequence:

(1) Disable the external interrupt which is selected.

(2) Change the active edge in interrupt edge selection register (in

case of CNTR0: Timer X mode register; in case of CNTR1:

Timer Y mode register).

(3) Clear the set interrupt request bit to “0”.

(4) Enable the external interrupt which is selected.

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