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M38270E1-XXXFP View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38270E1-XXXFP Datasheet PDF : 70 Pages
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MITSUBISHI MICROCOMPUTERS
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3827 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Real time port
control bit “1”
QD
P52
P52 data for real time port
Data bus
P52 direction register “0”
Latch
P52 latch
Real time port
control bit “1”
QD
P53
P53 data for real time port
P53 direction register “0”
Latch
P53 latch
Real time port
control bit “0”
“1”
Timer X mode register
write signal
f(XIN)/16
(f(XIN)/16 in low-speed modeV)
CNTR0 active Timer X operat-
edge switch bit
ing mode bits
“00”,“01”,“11”
Timer X stop
control bit
Timer X (low) latch (8)
Timer X write
control bit
Timer X (high) latch (8)
“0”
P54/CNTR0
Timer X (low) (8)
Timer X (high) (8)
“10”
“1”
Pulse width
measurement
mode CNTR0 active
edge switch bit “0” Q S
Pulse output mode
P54 direction register
“1”
P54 latch
T
Q
Timer Y operating mode bit
“00”,“01”,“10”
Pulse width HL continuously measurement mode
Pulse output mode
Rising edge detection
Falling edge detection
f(XIN)/16
(f(XCIN)!16 in φ = XCIN divided by 2)
Period
measurement mode
“11”
P55/CNTR1
CNTR1 active
edge switch bit “00”,“01”,“11”
“0”
Timer Y stop
control bit
Timer Y (low) latch (8)
Timer Y (low) (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
“1”
“10” Timer Y operating
mode bit
f(XIN)/16
(f(XCIN)/16 in φ = XCIN divided by 2)
Timer 1 count source
selection bit
“0”
Timer 1 latch (8)
XCIN
“1”
Timer 1 (8)
Timer 2 count source
selection bit
“0”
Timer 2 latch (8)
Timer 2 (8)
“1”
f(XIN)/16
(f(XCIN)!16 in φ=XCIN divided by 2)
Timer 2 write
control bit
Timer X
interrupt
request
CNTR0
interrupt
request
CNTR1
interrupt
request
Timer Y
interrupt
request
Timer 1
interrupt
request
Timer 2
interrupt
request
TOUT output
active edge
TOUT output
control bit
TOUT output switch bit
P43/φ/TOUT
control bit
“0”
QS
T
“1”
P43 direction register
P43 latch
Q
“0”
Timer 3 latch (8)
f(XIN)/16(f(XCIN)/16 in low-speed modeV)
Timer 3 (8)
“1”
Timer 3 count
source selection bit
Timer 3
interrupt
request
Fig. 17 Timer block diagram
21
 

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