M38270E1-XXXFP View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M38270E1-XXXFP

Single-chip 8-bit CMOS microcomputer. PROM 61440 bytes, RAM 2048 bytes. One time PROM version.

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3827 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by seventeen sources: seven external, nine inter-

nal, and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an

interrupt request bit and an interrupt enable bit, and is controlled

by the interrupt disable flag. An interrupt occurs if the correspond-

ing interrupt request and enable bits are “1” and the interrupt

disable flag is “0.” Interrupt enable bits can be set or cleared by

software. Interrupt request bits can be cleared by software, but

cannot be set by software. The BRK instruction interrupt and reset

cannot be disabled with any flag or bit. The I flag disables all inter-

rupts except the BRK instruction interrupt and reset. If several

interrupts requests occurs at the same time the interrupt with high-

est priority is accepted first.

Interrupt Operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The contents of the program counter and processor status

register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding

interrupt request bit is cleared.

3. The interrupt jump destination address is read from the vec-

tor table into the program counter.

sNotes

When the active edge of an external interrupt (INT0–INT2, CNTR0,

CNTR1) is set or when switching interrupt sources of ADT/A-D

conversion interrupt, the corresponding interrupt request bit may

also be set. Therefore, take following sequence:

(1) Disable the external interrupt which is selected.

(2) Change the active edge in interrupt edge selection register

(timer XY mode register when using CNTR0, CNTR1)

(3) Clear the set interrupt request bit to “0.”

(4) Enable the external interrupt which is selected.

Table 6 Interrupt vector addresses and priority

Interrupt Source Priority

Vector Addresses (Note 1)

High

Low

Reset (Note 2)

1

INT0

2

FFFD16

FFFB16

FFFC16

FFFA16

INT1

3

FFF916

FFF816

Serial I/O1

reception

Serial I/O1

transmission

Timer X

Timer Y

Timer 2

Timer 3

CNTR0

4

FFF716

5

FFF516

6

FFF316

7

FFF116

8

FFEF16

9

FFED16

10

FFEB16

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

CNTR1

Timer 1

INT2

11

FFE916

12

FFE716

13

FFE516

FFE816

FFE616

FFE416

Serial I/O2

14

FFE316

FFE216

Key input

15

(Key-on wake-up)

ADT

16

FFE116

FFDF16

FFE016

FFDE16

Interrupt Request

Generating Conditions

At reset

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of INT1 input

At completion of serial I/O1 data

reception

At completion of serial I/O1

transmit shift or when transmis-

sion buffer is empty

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or

falling edge of CNTR0 input

At detection of either rising or

falling edge of CNTR1 input

At timer 1 underflow

At detection of either rising or

falling edge of INT2 input

At completion of serial I/O2 data

transmission or reception

At falling of conjunction of input

level for port P2 (at input mode)

At falling of ADT input

A-D conversion

At completion of A-D conversion

BRK instruction

17

FFDD16

FFDC16

At BRK instruction execution

Notes1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

Valid when serial I/O1 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O2 is selected

External interrupt

(valid when an “L” level is applied)

Valid when ADT interrupt is se-

lected External interrupt

(Valid at falling)

Valid when A-D interrupt is se-

lected

Non-maskable software interrupt

18

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