M37754FFCGP View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
View to exact match
M37754FFCGP Datasheet PDF : 68 Pages
| |||
PRELIMINARY NSootimcee: pTahriasmisentroict alimfinitsalasrpeescuifbicjeactitotno. change.
MITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Parameter
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Limits
Min.
Max.
Unit
80
ns
40
ns
40
ns
160
ns
80
ns
80
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
TBiIN input cycle time
Parameter
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
Limits
Min.
Max.
Unit
16 × 109
f(XIN)
(400)
ns
8 × 109
f(XIN)
(320)
ns
8 × 109
f(XIN)
(200)
ns
4 × 109
f(XIN)
(160)
ns
8 × 109
f(XIN)
(200)
ns
4 × 109
f(XIN)
(160)
ns
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
Timer B input (Pulse width measurement mode)
Symbol
tc(TB)
TBiIN input cycle time
Parameter
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
Limits
Min.
Max.
Unit
16 × 109
f(XIN)
(400)
ns
8 × 109
f(XIN)
(320)
ns
8 × 109
f(XIN)
(200)
ns
4 × 109
f(XIN)
(160)
ns
8 × 109
f(XIN)
(200)
ns
4 × 109
f(XIN)
(160)
ns
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
A-D trigger input
Symbol
tc(AD)
tw(ADL)
Parameter
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Limits
Min.
Max.
Unit
1000
ns
125
ns
42
|
|
Share Link: 