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ADF4117BRUZ1 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADF4117BRUZ1
ADI
Analog Devices ADI
ADF4117BRUZ1 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4116/ADF4117/ADF4118
Pin No. Mnemonic
1
FLO
2
CP
3
CPGND
4
AGND
5
RFINB
6
RFINA
7
AVDD
8
REFIN
9
DGND
10
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DVDD
16
VP
PIN FUNCTION DESCRIPTIONS
Function
Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter band-
width. This will speed up locking of the PLL.
Charge Pump Output. When enabled, this provides the ±ICP to the external loop filter, which in turn drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path for the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF. See Figure 22.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 k. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal
oscillator or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.
TSSOP
PIN CONFIGURATIONS
Chip Scale Package
FLO 1
16 VP
CP 2
CPGND 3
15 DVDD
ADF4116
ADF4117 14 MUXOUT
AGND 4 ADF4118 13 LE
TOP VIEW
RFINB 5 (Not to Scale) 12 DATA
RFINA 6
11 CLK
AVDD 7
10 CE
REFIN 8
9 DGND
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4116
ADF4117
ADF4118
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
REV. 0
5
 

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