FREFIN
VP
POWER-DOWN CONTROL
VDD
7 15 16
AVDD DVDD VP CE 2
8 REFIN
CP
FLO 1
ADF4116/
ADF4117/
ADF4118
10k⍀
LOOP
FILTER
ADF4116/ADF4117/ADF4118
S VDD
IN ADG702
D GND
100pF
RFOUT
VCC
VCO
GND
100pF 18⍀ 18⍀
18⍀
RFINA 6 100pF
RFINB 5
51⍀
3 49
100pF
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 27. Local Oscillator Shutdown Circuit
0.1F
REFIO
IOUTA
MODULATED
DIGITAL
DATA
IOUTB
AD9761
TXDAC
QOUTA
FS ADJ QOUTB
2k⍀
LOW-PASS
FILTER
LOW-PASS
FILTER
OSC 3B1-13M0
TCXO
RSET
REFIN
CP
SERIAL
DIGITAL
NTERFACE
ADF4118
680pF
RFINB RFINA
10k⍀
1k⍀ 18pF
6.8nF
IBBP
IBBP
100pF
VOUT
AD8346
QBBP
QBBP
LOIN
LOIP
100pF
100pF
RFOUT
18⍀
VCO190-1960T
100pF 18⍀
18⍀
100pF
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS
ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 28. Direct Conversion Transmitter Solution
INTERFACING
The ADF4116 family has a simple SPI-compatible serial inter-
face for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table II for the Latch
Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems which will have typical lock times in hun-
dreds of microseconds.
REV. 0
–19–